Imitation using artificial tools of some of the incredible human brain capacities for cognitive processes
will certainly be the next big challenge in the revolution of information technology. A few days-old baby is
able to interpret and analyse sequences of images in a fraction of second whereas such apparently simple
tasks are still out of the reach of the most powerful digital computers. In order to solve some problems of
artificial intelligence, complex computational models called Artificial Neural Networks (ANNs) have been
proposed based on the brain architecture. Even if ANNs with multiple neural layers are extremely powerful,
they loose the speed, fault tolerance and low power consumption provided by their originally analog and
parallel architecture when they are implemented as software simulations. Thus the development of new
hardware devices having a brain-inspired massively parallel, dynamical architecture and radically different
from contemporary IT technology is today a top objective for computer scientists, neuro-scientists and
hardware designers. Since the number of synapses is order of magnitudes larger than the number of neurons,
the development of neuromorphic circuits for complex operations relies on the ability to build nano-scale
synapses. Improvement of the performances of existing hardware ANNs are limited by their need of a large
number of electronic components for the implementation of each synapse, including SRAMs blocks to store the
weights.
To use a memristor device as ideal artificial nano-synapse for development of future hardware ANNs is the
main focus and the originality of the NanoBrain project. Our basic element, the memristor, is an ultrasmall
non-linear dynamical and non-volatile electrical resistance. Such device has an intrinsic memory effect that
allows a straight implementation of the synaptic plasticity, as demonstrated by a Hewlett-Packard team in
2008 with devices based on electromigration in a TiOx thin layer. We are fabricating and optimizing new fast,
endurant, highly integrable and CMOS-compatible memristor devices, based on alternative concepts : spintronics
and ferroelectricity. Our final goal will be to demonstrate the efficiency of these new nano-synapses by
integrating them into functional hardware Neural Networks.
ERC starting grant NanoBrain
Spin-transfer induced domain wall motion in a spin valve structure is by nature a memristive effect. The resistance of the Giant Magneto-Resistance
device shown in (a) depends on the domain wall position x between the
contacts. For current densities above a threshold value Jc, defined in particular by the initial pinning of the DW, the DW propagation
speed is proportional to the injected current. Spin-transfer can generate domain wall speeds above 100 m/s, which means that the resistance
of a sub-micron "spin memristor" can be modified in a few nanoseconds. The displacement x(t) is proportionnal to I.t = q.
The device resistance depends on the charge, and not only on the current, which confers this memristor its memory effect.
This device is a multi-state analog resistance controlled by the injected charge, via spin transfer induced DW motion. When the current is set to
zero, the device remains at its last resistance value. By changing the initial magnetic configuration, the memristor can be changed from an
"inhibitory" (the resistance increases) to an "excitatory" (the resistance decreases) artificial synapse.
The problem with the device presented above is the small resistance variations obtained when the domain wall is propagating, since the the GMR ratio
is only a few percent. In order to increase the resistance changes, the tunnel magnetoresistance effect can be used, which requires to replace the
metallic normal spacer by a thin insulating barrier, in the manner of the DW-RAM.
Fabricating a two-terminal memristor device using a magnetic tunnel
junction implies to be able to move a
domain wall back and forth by vertical current injection, as sketched in (b).
In order to demonstrate the domain wall motion by vertical spin injection, we use a magnetic tunnel junction with a thin MgO barrier
(1.1 nm thick), a top (CoFe 1nm/NiFe 4 nm) free electrode and a CoFeB 3 nm reference electrode. The tunnel junction cross section has a specific
U-shape, with a wire width of 210 nm.
This geometry facilitates DW creation close to the wire edge, as shown by the micromagnetic simulations in
the inset of the figure. In our convention, a positive current corresponds to electrons flowing from the reference to the free layer.
We show the resistance versus current curve obtained with vertical current injection at different applied magnetic fields.
The domain wallis initially created in the wire. In addition to the expected bias dependence of the tunnel resistance, we clearly observe
irreversible resistance jumps. By sweeping the current to positive values, the resistance is switched to a lower resistance state
corresponding to another domain wall position, stable at zero current. By applying a negative currents, the domain wall moves in the
opposite direction. We thus demonstrate the possibility to move a domain wall by perpendicular
dc current injection. The current densities corresponding to the DW motion are lower than 4 106 A.cm-2, as can be seen from
the top x axis of the figure. The use of perpendicular current injection therefore allows to reduce the current densities by a factor 100 compared
to the classical lateral current injection. These recent results pave the way towards the implementation of fast and robust spintronic memristors.
