The memristor, for « memory-resistor », has been originally defined in 1971 by Leon Chua through the expression v = M(q) I. The memristance, M, depends on the charge, which confers this device its memory effect. Here we will use the most general definition of a memristor: a non-volatile, non-linear, analog and tunable nano-resistor.

The ideal memristor is small (< 50 x 50 nm²), and has a large OFF/ON ratio (> 1000). These features open the possibility to build ultra-dense resistive matrices of memristors, called crossbar arrays, that can then be stacked on top of a CMOS underlayer.

Almost all existing memristor concepts are based on physical phenomena involving defects or deep material structural changes to induce the resistance variations: fuse/antifuse, nano-ionic or thermal processes (RedOx RAMs, Phase Change memories). Reliability and endurance issues can then appear due to the large local heating and the need of a forming step. In addition, the physical phenomena at stake are complex and far from being understood, making it difficult to model and predict the devices behaviour. While their performances may be sufficient for certain class of memories, the endurance and cyclability of these ReRAMs may not be large enough for applications where the devices need to be written and rewritten repetitively. This is the case for cache memories, and for memristor synapses in unsupervised on-line neural networks where learning and adaptation is constant. There is therefore a practical interest to develop novel types of memristors, based on different physical concepts.

This is why we develop “purely electronic” memristors, in other words nano-devices where the resistance changes are obtained through electron mediated phenomena at interfaces. These memristors promise an increased endurance and reliability, since the material structure is preserved, but also a faster commutation speed. In 2009, we have patented two new concepts: the spin torque memristor and ferroelectric memristor. Both are based on emerging digital memory concepts, subject of intense academic and industrial developments. The “spin torque” memristor is derived from the Spin Torque MRAM, that should be on the market in 2013, and is foreseen as DRAM’s replacement as cache memory. The building block of ST-MRAM, the magnetic tunnel junction (ferromagnet/insulating barrier/ferromagnet), relies on magnetization switching. The “ferroelectric” memristor is based on the ferroelectric resistive RAM. Here the brick is the ferroelectric tunnel junction: an insulating ferroelectric ultrathin barrier sandwiched between two metallic electrodes. The commutation of polarization in the barrier when a voltage is applied across the junction can give rise to large resistance changes. The idea is to transform these binary memories in multi-state, quasi-analog memristors. For that purpose, we play with the mechanisms of ferromagnetic and ferroelectric commutation. We design the devices in such way that switching occurs through non-uniform magnetic or ferroelectric domain configurations. The device resistance is then directly related to the details of this domain configuration.

The building block of the ferroelectric memristor is the ferroelectric tunnel junction. If the screening lengths of the electrodes are different, then, when the polarization in the barrier is reversed, the effective barrier height is changed, giving rise to large resistance variations (several orders of magnitude) between the low R_ON and high R_OFF resistance states. In these devices, the polarization does nor switch abruptly from up to down. On the contrary, the ferroelectric reversal occurs through the formation and propagation of ferroelectric domains of opposed polarity. During this process, the resistance is neither R_ON or R_OFF, but in between. This is why multi-resistance states can be obtained : when the voltage is cycled, the ferroelectric domain configuration varies accordingly.

In addition, a very fine tuning of the resistance can be achieved thanks to the very small ferroelectric domain size (approximately 5 nm) in the ultra-thin (2 nm) barrier of BaTiO₃. Using PFM imaging, we can measure the resistance and the domain configuration at the same time. We have shown that our data can be perfectly explained by a conduction in parallel through the up and down domains. 10 ns pulses of a few volts allow to vary the resistance states controllably. By tuning the materials in the junction stack, we have recently obtained resistance variations over 4 orders of magnitude.

The large OFF/ON ratios over two orders of magnitude, fast switching below 10 ns, combined to the purely electronic operation, make the ferroelectric memristor an excellent candidate for future integration in large scale crossbar arrays and neuromorphic applications. This is our goal in the EU ERC NanoBrain and French ANR P2N MHANN projects.

The spin torque memristor is based on a magneto-resistive trilayer with a magnetic domain wall in its free layer. The trilayer resistance depends on the relative proportion of parallel and anti-parallel domains, which is set by the domain wall position. The more the domain wall is to the left, the closer the configuration is to the parallel state, the smaller the resistance. Using the spin torque effect, it is possible to manipulate the position of a magnetic DW. The domain wall displacement Δx then depends on the amplitude j of the injected current as well as the pulse duration Δt: Δx = j.Δt = Δq. Therefore the resistance depends on the charge, and a spin torque memristor is obtained. The classical way to move a DW by spin transfer is to inject the current laterally. If the trilayer is a metallic spin-valve, the same lateral geometry allows reading the device resistance, thanks to Current-In-Plane (CIP) magneto-resistance. Some authors have proposed to use this geometry to implement the spin torque memristor. Unfortunately, the CIP magnetoresistance ratios in spin-valves are limited to a few %, which would give rise to OFF/ON ratios well below 1. This is much too low for discriminating the different states in a real-world application, and even more for implementing these devices in crossbar arrays.

The solution to increase the OFF/ON ratio up to 6 and more is to use magnetic tunnel junctions. In that case reading can only be achieved by applying the probe current vertically across the junction. The spin torque memristor concept that we propose is based on vertical writing as well. This has two advantages. First, since the reading and writing paths are the same, we keep a two-terminal, easy to scale down, conform to definition memristor. Secondly, as we have shown, spin torque induced domain wall motion by vertical injection is much more efficient than the lateral scheme.

In order to give the proof of concept of our spin torque memristor, we have used a magnetic tunnel junction with a thin MgO barrier (1.1 nm thick), a top (CoFe 1nm/NiFe 4 nm) free electrode and a CoFeB 3 nm reference electrode. The tunnel junction cross section has a specific U-shape, which facilitates DW preparation, with a wire width of 100-200 nm.

Three resistance states are obtained, corresponding to three stable positions of the DW, implementing a three state spintronic memristor. These 3 configurations, reproducible from sample to sample, are due to the specific arc shape of the junction. The vertical current injection allows displacing the DW to the left or to the right depending on the current sign. The very low critical current densities of a few 10⁶ A.cm^-2 confirm the orders of magnitude gain compared to the lateral injection scheme (which requires 10⁸ A.cm^-2 to move a DW).

We have recently shown that the commutation is extremely fast, with switching times below the nanosecond. For current densities of 10⁷ A.cm^-2, the DW velocities exceed 600 m/s.

By fabricating a 3 state spin torque memristor, we have given the proof of concept of our device. The purely electronic switching, with reasonable current densities of a few 10⁶ A.cm^-2, combined with the sub-ns commutation times, make this device very promising for applications were the number of writing cycles will be very large. To go beyond the proof of concept we are now working on engineering more resistance states (more DW positions), and decreasing the currents. The main drawback of the spin torque memristor is the low OFF/ON ratios, limited to about 6 with today’s tunnel junctions, preventing their use in large crossbar arrays. Nevertheless, due to the strong research efforts to improve ST-MRAM technology, the TMR ratios keep increasing, and we are still far from the theoretical limit, which predicts R_AP/R_P over 100. In addition, the spin torque memristor has another great advantage compared to other technologies: it can be easily combined with other spin torque based devices with complementary functionalities to implement novel hybrid CMOS/Spintronics architectures. This is one of our goals in the EU ERC NanoBrain project.